1. Field of the Invention
The present invention relates to a D/A conversion (digital-to-analog conversion) circuit (DAC: Digital-Analog Converter). The invention relates, more particularly, to a DAC used in the driving circuit of a semiconductor device and, further, to a semiconductor device using this DAC.
2. Description of the Related Art
Recently, the technique of fabricating a semiconductor device in which semiconductor thin films are formed on a cheap glass substrate, such as, e.g., the technique of fabricating thin film transistors (TFTs) is being rapidly developed. The reason therefor is that the demand for semiconductors (particularly, active matrix liquid crystal display devices and EL display devices) is growing.
An active matrix liquid crystal display device is constituted in such a manner that, in each of several tens of millions to several hundreds of millions of pixel regions disposed in a matrix-like state, a TFT is disposed, so that the charges coming into and going out from the respective pixel elements are controlled by the switching function of the TFTs.
Among such active matrix liquid crystal display devices, a digital driving type active matrix liquid crystal display device is attracting attention as the display devices are becoming more and more precise and minute and as their picture quality is becoming higher and higher.
FIG. 15 shows an outline of the structure of a conventional digital driving type active matrix liquid crystal display device. The conventional digital driving type active matrix liquid crystal display device is comprised, as shown in FIG. 15, of a source signal line side shift register 1401, address lines (a to d) 1402 for the digital signals inputted from the outside, latch circuits 1 (LAT1) 1403, latch circuits 2 (LAT2) 1404, a latch pulse line 1405, D/A conversion circuits 1406, gradation voltage lines 1407, source signal lines (data lines) 1408, a gate signal line side shift register 1409, gate signal lines (scanning lines) 1410 and pixel TFTs 1411. A 4-bit digital driving type active matrix liquid crystal display device is taken up by way of example. The latch circuits 11403 and the latch circuits 21404 (LAT1 and LAT2) are each shown in the state in which four latch circuits are put together for convenience"" sake.
The digital signals fed from the outside to the digital signal address lines (a to d) 1402 are successively written into all the LAT11403 in accordance with the timing signals from the source signal line side shift register 1401. In this specification, all the LAT1 put together will be genetically called LAT1 group.
The length of time required for completing the writing of the digital signals into the LAT1 group is called one line period. In other words, the time interval from the point of time when the writing of the digital signals inputted from the outside into the LAT1 at the leftmost side is started to the point of time when the writing of the digital signals inputted from the outside into the LAT1 at the rightmost side is completed, is one line period.
After the writing of the digital signals into the LAT1 group is terminated, the digital signals thus written into the LAT1 group are simultaneously transmitted and written into all the LAT21404, in tune with the operating timing of the source signal line side shift register 1401, when a latch signal is inputted to the latch pulse line 1405. In this specification, all the LAT2 put together will be genetically called LAT2 group.
Into the LAT1 group which has finished the transmission of the digital signals to the LAT2 group, the writing of the digital signals again fed to the digital decoder address lines (a to d) 1402 is successively carried out in accordance with the signals from the source signal line side shift register 1401.
In step with the start of the second one-line period, the digital signals previously sent out to the LAT2 group are inputted to the D/A conversion circuits 1406 and converted into analog graduation voltage signals corresponding to the digital signals and then fed to the source signal lines 1408.
The analog gradation voltage signals are fed to the corresponding source signal lines 1408 for the one-line period. By the scanning signals outputted from the gate signal line side shift register 1409, the switching of the corresponding pixel TFTs 1411 is carried out, and, by the analog graduation voltage signals from the source signal lines 1411, the liquid crystal molecules are driven.
By repeating the above-mentioned operation a number of times equal to the scanning line number, one picture (one frame) is formed. Generally, in an active A matrix liquid crystal display device, the rewrite of 60 frame images is effected for one second.
Here, the known A/D converter circuits used in the above-mentioned digital driving circuit will be described. FIG. 16 will be referred to.
A known 4-bit D/A conversion circuit comprises switches (sw0 to sw15) and gradation voltage lines (V0 to V15). This 4-bit D/A conversion circuit is constituted in such a manner that, by the 4-bit digital signals fed from the LAT2 group 1404 in the digital driving type active matrix liquid crystal display device shown in FIG. 15, one of the switches (sw0 to sw15) is selected, and, from the gradation voltage line connected to the thus selected switch, the voltage is fed to the source signal line 1408.
In case of the known 4-bit D/A conversion circuit which is now being described, the number of the switches is 16, and the number of the graduation voltage lines is 16. In an actual active matrix type liquid crystal display device, the area of the switches themselves is large. Further, the D/A conversion circuit shown in FIG. 16 is provided at a rate of one to one source signal line, so that the area of the whole driving circuit becomes large.
Another example of the known 4-bit D/A conversion circuit will next be taken up. The 4-bit D/A conversion circuit shown in FIG. 17 is constituted in such a manner that, as in case of the 4-bit D/A conversion circuit described above, one of a plurality of switches (sw0 to sw15) is selected by the 4-bit digital signal fed from the LAT2 group 1404, and, from the gradation voltage line connected to the thus selected switch, the voltage is fed to the source signal line 1408.
In the D/A conversion circuit shown in FIG. 17, the graduation voltage lines are five in number (V0 to V4) and thus are smaller in number than those of a 4-bit D/A conversion circuit as shown in FIG. 16. However, the number of the switches is still sixteen. Therefore, it is difficult to reduce the area of the whole driving circuit.
In case of a D/A conversion circuit which converts 4-bit digital signals into an analog gradation voltage signal as described here, if the bit number increases, the number of the switches is exponentially increased. In other words, in the known D/A conversion circuit which converts n-bit digital signals into an analog gradation signal, 2n switches become necessary. Therefore, it is difficult to hold down the area of the driving circuit.
In case of the driving circuit which includes D/A conversion circuits as mentioned above, it is difficult to hold down its area, which becomes a cause for hindering the miniaturization of semiconductor devices, particularly, active matrix liquid crystal display devices.
Further, for making semiconductor display devices highly precise and minute, the number of the pixels must be increased, that is, the number of the source signal lines must be increased. However, if the source signal lines are increased in number, then the number of the D/A conversion circuits is also increased as mentioned above, and thus, the area of the driving circuit is increased, which is a cause for impeding the realization of a high precise and minute structure.
For the reasons mentioned above, there is a growing demand for keeping small the area of an D/A conversion circuit.
Further, besides the above-mentioned resistance division type DAC, there is a capacitance division type DAC in which the resistance division is made by the capacitance. In order to operate the capacitance division type DAC, there are needed the period of time for accumulating charges in the capacitance and the period of time for discharging the charges accumulated in the capacitance to reset them to the same charges as the GND (ground), so that the operating speed is slow.
Thus, the present invention has been achieved in view of the above-mentioned problems, and it is the object of the invention to hold down the area of a D/A conversion circuit to a small value.
The DAC according to the invention comprises a resistor A group consisting of n resistors A0, A1, . . . , Anxe2x88x921 which correspond to n-bit digital signals, respectively, and a resistor B group consisting of n resistors B0, B1, . . . , Bnxe2x88x921. The general expression of the resistance values of the resistor A group and the resistor B group is 2nxe2x88x921R (wherein n stands for a natural number which is 1 or greater, and R stands for a positive number). Further, the DAC according to the invention includes a switch SWa group consisting of switches SWa0, SWa1, . . . , SWanxe2x88x921 which correspond to the respective n-bit digital signals and a switch SWb group consisting of n switches SWb0, SWb1, . . . , SWbnxe2x88x921. The DAC according to the invention further includes two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, which are maintained at potentials different from each other.
When the switches of the switch SWa group are turned on, the power-supply voltage line L and an output line are connected to each other through the resistor A group consisting of n resistors A0, A1, . . . Anxe2x88x921. Further, when the switches of the switch SWb group are similarly turned on, the power-supply voltage line H and the output line are connected through the resistor B group consisting of n resistors B0, B1, . . . , Bnxe2x88x921.
Conversely, if the switches of the switch SWa group are turned off, then the connection between the power-supply voltage line L and the output line is cut off. Further, if similarly the switches of the switch SWb group are turned off, then the connection between the power-supply voltage line H and the output line is cut off.
The switch SWa group is controlled by the n-bit digital signals inputted from the outside, and the switch SWb group is controlled by the inverted signals of the n-bit digital signals. Then an analog gradation voltage signal corresponding to the inputted n-bit digital signals is outputted through the output line.
The DAC according to the present invention will now be described on the basis of certain aspects of the invention.
FIG. 1 shows the DAC circuit according to Embodiment Mode 1. The DAC of the invention shown in FIG. 1 converts n-bit digital signals into an analog graduation voltage signal. In the present invention, n stands for a natural number.
As shown in FIG. 1A-FIG. 1D, the DAC according to the invention includes n resistors A0, A1, . . . , Anxe2x88x921 and n resistors B0, B1, . . . , Bnxe2x88x921. The n resistors A0, A1, . . . Anxe2x88x921, put together, will be generically called register A group. Further, the n resistors B0, B1, . . . , Bnxe2x88x921, put together, will be generically called register B group.
The respective resistors constituting the resistor A group are as follows: A1=R, A2=2R, A3=22R, . . . , Anxe2x88x921=2nxe2x88x921R. Further, the respective resistors constituting the resistor B group are as follows: B1=R, B2=2R, B3=22R, . . . , Bnxe2x88x921=2nxe2x88x921R. In the present invention, R is a constant for standing for a resistance value.
In the invention, the n resistors A0, A1, . . . , Anxe2x88x921 and the n resistors B0, B1, . . . , Bnxe2x88x921 each have two or more terminals. As these terminals, there are input and output terminals for inputting to the resistor and outputting from the resistor, and, besides them, a common terminal which is common for inputting to and outputting from the resistor. In the invention, the two input and output terminals of the resistors will hereinafter be referred to as the ends of the resistors.
Further, the DAC according to the invention includes n switches SWa0, SWa1, . . . , SWanxe2x88x921 and n switches SWb0, SWb1, . . . , SWbnxe2x88x921. The n switches SWa0, SWa1, . . . , SWanxe2x88x921, put together, will be generically called switch Swa group. Further, the n switches SWb0, SWb1, . . . , SWbnxe2x88x921, put together, will be generically called switch group SWb. Further, the switch SWa group and the switch SWb group, put together, will be generically called switch SW group. In this Embodiment Mode, the internal resistance of the switch SW group is regarded as 0, but it is also permissible to make the circuit design by taking the internal resistance of the switch SW group into account.
In the invention, the n switches SWa0, SWa1, . . . , SWanxe2x88x921 and the n switches SWb0, SWb1, . . . , SWbnxe2x88x921 each have input and output terminals for inputting to the switch and for outputting from the switch. Further, in some cases, the switches each have, besides the input and output terminals, a common terminal which is common for inputting to and outputting from the switch. In the invention, the two terminals, the input and output terminals, of the switches will be called the ends of the switches.
Further, the DAC according to the invention includes an output line, a power-supply voltage line L, and a power-supply voltage line H. From the output line that the DAC has, an analog gradation voltage signal resulting from the conversion of digital signals is outputted. The output potential of the analog gradation voltage signal outputted from the output line will be called Vout.
The power-supply voltage line L and the power-supply voltage line H are connected to a power supply provided outside the DAC and maintained at constant potentials. The power-supply voltage line L is maintained at a power-supply potential VL, and the power-supply voltage line H is maintained at a power-supply potential VH.
The power-supply potential VL and the power-supply potential VH are both alike based on the ground (GND) potential.
In this specification, to connect means to electrically conduct. To electrically conduct is a matter of degree. In case that what is supplied with electricity fulfills its object function or in case that the object function of what is supplied with electricity is spoiled, it is defined that electrical conduction is effected. Further, in this specification, connection being cut off is defined as a state in which electrical conduction is not effected.
As for the relationship between the power-supply potential VH and the power-supply potential VL, in case of VH less than VL and in case of VH greater than VL, analog signals which are inverted with respect to each other are outputted as the output potentials Vout. Here, the output in case of VH greater than VL, is set as positive phase, while the output in case of VH less than VL is set as opposite phase.
Here, the circuit arrangement of the DAC according to the invention will be described.
Both-ends of the resistor A0 are respectively connected to the switch SWa0 and the output line. That end of the switch SWa0 which is not connected to the resistor A0 is connected to the power-supply voltage line L.
Further, both ends of the resistor A1 are respectively connected to the switch SWa1 and the output line. That end of the switch SWa1 which is not connected to the resistor A1 is connected to the power-supply voltage line L.
Further, both ends of the resistor A2 are respectively connected to the switch SWa2 and the output line. That end of the switch Swa2 which is not connected to the resistor A2 is connected to the power-supply voltage line L.
Similarly, both ends of the resistor Anxe2x88x921 are respectively connected to the switch SWanxe2x88x921 and the output line. That end of the switch SWanxe2x88x921 which is not connected to the resistor Anxe2x88x921 is connected to the power-supply voltage line L.
As mentioned above, both ends of the resistors A0, A1, . . . , Anxe2x88x921 are respectively connected to the respective switches SWa0, SWa1, . . . SWanxe2x88x921 and the output line. Those ends of the respective switches SWa0, SWa1, . . . , SWanxe2x88x921 which are not connected to the respective resistors A0, A1, . . . , Anxe2x88x921 are connected to the power-supply voltage line L.
The relationship between the resistors B0, B1, . . . , Bnxe2x88x921 and the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is also similar to the relationship between the resistors A0, A1, . . . , Anxe2x88x921 and the switches SWa0, SWa1, . . . , SWanxe2x88x921. That is, both ends of the respective resistors B0, B1, . . . , Bnxe2x88x921 are connected to the respective switches SWb0, SWb1, . . . , SWbnxe2x88x921 and the output line. The respective ends of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 which ends are not connected to the resistors B0, B1, . . . , Bnxe2x88x921 are connected to the power-supply voltage line H.
Next, the operation of the DAC according to the invention will be described.
When the switch SWa0 is turned on, the power-supply voltage line L and the resistor A0 are connected to each other. In other words, when the switch Swa0 is turned on, that end of the resistor A0 which is connected to the switch SWa0 is maintained at the same potential as the power-supply potential VL. Conversely, if the switch SWa0 is turned off, then the connection between the power-supply voltage line L and the resistor A0 is cut off.
Further, if the switch Swa1 is turned on, the power-supply voltage line L and the resistor A1 are connected to each other. In other words, if the switch SWa1 is turned on, then that end of the resistor A1 which is connected to the switch SWa1 is maintained at the same potential as the power-supply potential VL. Conversely, if the switch SWa1 is turned off, then the connection between the power-supply voltage line L and the resistor A1 is cut off.
Further, if the switch SWa2 is turned on, then the power-supply voltage line L and the resistor A2 are connected to each other. In other words, if the switch SWa2 is turned on, then that end of the resistor A2 which is connected to the switch SWa2 is maintained at the same potential as the power-supply potential VL. Conversely, if the switch SWa2 is turned off, then the connection between the power-supply voltage line L and the resistor A2 is cut off.
Similarly, if the switch SWanxe2x88x921 is turned on, then the power-supply voltage line L and the resistor Anxe2x88x921 are connected to each other. In other words, if the switch SWanxe2x88x921 is turned on, then that end of the resistor Anxe2x88x921 which is connected to the switch SWanxe2x88x921 is maintained at the same potential as the power-supply potential VL. Conversely, if the switch SWanxe2x88x921 is turned off, then the connection between the power-supply voltage line L and the resistor Anxe2x88x921 is cut off.
As mentioned above, if each of the switches SWa0, SWa1, . . . , SWanxe2x88x921 is turned on, then the power-supply voltage line L and each of the resistors A0, A1, . . . , Anxe2x88x921 are connected to each other. In other words, if each of the switches SWa0, SWa1, . . . SWanxe2x88x921 is turned on, then that end of each of the resistors A0, A1, . . . , Anxe2x88x921 which is connected to each of the switches SWa0, SWa1, . . . , SWanxe2x88x921 is maintained at the same potential as the power-supply potential VL. Conversely, if each of the switches SWa0, SWa1, . . . , SWanxe2x88x921 is turned off, then the connection between the power-supply voltage line L and each of the resistors A0, A1, . . . , Anxe2x88x921 is cut off. Similarly, if each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is turned on, then the power-supply voltage line H and each of the resistors B0, B1, . . . , Bnxe2x88x921 are connected to each other. In other words, if each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is turned on, then that end of each of the resistors B0, B1, . . . , Bnxe2x88x921 which is connected to each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is maintained at the same potential as the power-supply potential VH. Conversely, if each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is turned off, then the connection between the power-supply voltage line H and each of the resistors B0, B1, . . . , Bnxe2x88x921 is cut off.
The ON or OFF control of the switch SWa group and the switch SWb group is determined depending on the digital signal Da0, Da1, . . . , Danxe2x88x921 inputted to the DAC. The digital signals Da0, Da1, . . . , Danxe2x88x921, all put together, will be generically called digital signals Da.
The value of the digital signal is either Hi or Lo. For the convenience of description, the value of the digital signal when it is Hi will be defined as 1, while the value of the digital signal when it is Lo will be defined as 0. The digital signal is defined in such a manner that Da0 is the least significant bit (LSB), and Danxe2x88x921 is the most significant bit (MSB).
Further, the signals resulting from the inversion of the digital signals Da0, Da1, . . . , Danxe2x88x921 will be designated as DB0, DB1, . . . , Dbnxe2x88x921. Thus, it follows that, if Da0 is 1, then Db0 is 0, and, conversely if Da0 is 0, then Db0 is 1. The digital signals DB0, DB1, . . . , Dbnxe2x88x921, all put together, will be generically called a digital signal Db. If the digital signal Da is inputted to the DAC, then the digital signal Da is inputted to the switches SWa0, SWa1, . . . SWanxe2x88x921, and the digital signal Db is inputted to the switches SWb0, SWb1, . . . , SWbnxe2x88x921.
If the digital Da which is inputted to each of the switches SWa0, SWa1, SWanxe2x88x921 is assumed to be 1, then the switches SWa0, SWa2, . . . , SWbnxe2x88x921 are each turned on. The digital signal Db which is inputted to each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is the inversion of the digital signal Da and thus 0, so that the switches SWb0, SWb1, . . . , SWbnxe2x88x921 are each turned off. Conversely, if the digital signal Da inputted to each of the switches SWa0, SWa1, . . . , SWanxe2x88x921 is 0, then the switches SWa0, SWa1, . . . , SWanxe2x88x921 are each turned off. The digital signal Db which is then inputted to each of the switches SWb0, SWb1, . . . , SWbnxe2x88x921 is the inversion of the digital signal Da and thus 1, so that the switches SWb0, SWb1, . . . , SWbnxe2x88x921 are each turned on.
In this way, the switch SWa group and the switch SWb group are operatively associated with each other.
Let""s examine the digital signal Da0 being the first bit; if the digital signal Da0=1 is inputted to the DAC, then the Da0 is inputted to the switch SWa0 corresponding to the digital signal Da0, and the switch SWa0 is turned on. As a result, the power-supply potential VL of the power-supply voltage line L is applied to the resistor A0 corresponding to the switch Swa0.
When Da0=1, Db0=0. The digital signal Db0 is inputted to the corresponding switch SWb0, so that the switch SWb0 is turned off. As a result, the resistor B0 corresponding to the switch SWb0 is disconnected from the power-supply voltage line H.
To the digital signals, Da1, Da2, . . . , Danxe2x88x921, the same thing as mentioned about the digital signal Da0 above, also applies.
The operation performed by the DAC of the present invention in case that the digital signals Da inputted to the DAC are all 1, will be described by the use of FIG. 1A.
In case that the digital signals Da (Da0, Da1, . . . , Danxe2x88x921) inputted are all 1, the switches SWa0, SWa1, . . . , SWanxe2x88x921 are all turned on, and the output line is connected to the power-supply voltage line L through each of the resistors A0, A1, . . . , Anxe2x88x921. The then digital signals Db (DB0, DB1, . . . , Dbnxe2x88x921) are all 0, and thus, the switches SWb0, SWb1, . . . , SWbnxe2x88x921 are turned off, so that the output line is brought into a state disconnected from the power-supply voltage line H.
As a result, the power-supply potential VL of the power-supply voltage line L is outputted intact from the output line. The output potential Vout from the output line of the DAC becomes Vout (Da0=Da1= . . . =Danxe2x88x921=1)=VL.
The operation performed by the DAC of the invention when the digital signals Da inputted to the DAC are all 0, will be described by the use of FIG. 1B.
In case that the digital signals Da inputted are all 0, the switches SWa0, SWa1, SWaxe2x88x921 are all turned off, and the output line is brought into a state disconnected from the power-supply voltage line L. Since the digital signals Db are all 1, the switches SWb0, SWb1, . . . , SWbnxe2x88x921 are all turned on, and the output line is connected to the power-supply voltage line H through each of the resistors B0, B1, . . . , Bnxe2x88x921.
As a result, the power-supply potential VH of the power-supply voltage line H is directly outputted from the output line. The output potential Vout from the output line of the DAC becomes Vout (Da0=Da1= . . . =Danxe2x88x921=0) =VH.
The operation of the DAC according to the invention in case that, of the digital signals Da inputted to the DAC, only Da0 is 0, while Da1, Da2, . . . , Danxe2x88x921 are all 1, will be described by the use of FIG. 1C.
Since Da0 is 0, SWa0 is turned off, while SWb0 is turned on, and the output line is connected to the power-supply voltage line H through the resistor B0. On the other hand, since Da1, Da2, . . . , Danxe2x88x921 are all 1, SWa1, SWa2, . . . , SWanxe2x88x921 are all turned on, while, conversely, SWb1, SWb2, . . . , SWbnxe2x88x921 are all turned off, and thus, the output line is connected to the power-supply voltage line L through the resistors A1, A2, . . . , Anxe2x88x921.
Of the resistors A0, A1, . . . , Anxe2x88x921, the combined resistance of all those resistors (in this case, the resistors A1, A2, . . . Anxe2x88x921 correspond to those resistors) which are connected to the switches SWa1, SWa2, . . . , SWanxe2x88x921 that are in ON state, is assumed to be AT. Further, of the resistors B0, B1, . . . , Bnxe2x88x921, the combined resistance of all those resistors (in this case, the resistor B0 corresponds to those resistor) which are connected to the switch SWb0 that is in ON state, is assumed to be BT.
The reciprocal number of the combined resistance AT is equal to the sum of the reciprocal numbers of the respective resistors A1, A2, . . . , Anxe2x88x921 connected to the switches SWa1, SWa2, . . . , SWanxe2x88x921 which are in ON state. (Equation 1)
                                                                        1                                  A                  T                                            =                              xe2x80x83                            ⁢                                                1                                      A                    1                                                  +                                  1                                      A                    2                                                  +                ⋯                +                                  1                                      A                                          n                      -                      2                                                                      +                                  1                                      A                                          n                      -                      1                                                                                                                                              =                              xe2x80x83                            ⁢                                                1                                      2                    ⁢                    R                                                  +                                  1                                                            2                      2                                        ⁢                    R                                                  +                ⋯                +                                  1                                                            2                                              n                        -                        2                                                              ⁢                    R                                                  +                                  1                                                            2                                              n                        -                        1                                                              ⁢                    R                                                                                                          (        1        )            
By solving the equation 1 with respect to AT, the equation 2 is obtained.
                              ∴                      A            T                          =                                            2                              n                -                1                                                                    2                                  n                  -                  2                                            +                              2                                  n                  -                  3                                            +              ⋯              +              2              +              1                                ⁢                      xe2x80x83                    ⁢          R                                    (        2        )            
Further, similarly, the reciprocal number of the combined resistance BT is equal to the reciprocal number of the resistor B0 connected to the switch Swb0 that is in ON state. (Equation 3)
                              1                      B            T                          =                              1                          B              0                                =                      1            R                                              (        3        )            
By solving the equation 3 with respect to BT, the equation 4is obtained.
∴BT=Rxe2x80x83xe2x80x83(4)
By the use of the combined resistance AT and the combined resistance BT evaluated by the equation 2 and the equation 4, the output potential Vout (Da0=0, Da1=Da2 . . . Danxe2x88x921=1) from the output line of the DAC is evaluated. The output potential Vout (Da0=0, Da1=Da2= . . . =Danxe2x88x921=1) is what results from dividing the combined resistance AT of the equation 2 by the sum of the combined resistance AT of the equation 2 and the combined resistance BT of the equation 4and then multiplying the thus obtained quotient by the difference between the power-supply potential VH and the power-supply potential VL. (Equation 5)
                              V          OUT                =                                                            A                T                                                              A                  T                                +                                  B                  T                                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                =                                    1              2                        ·                                          2                n                                                              2                  n                                -                1                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                                          (        5        )            
In this way, by the ON/OFF operation of the switches, the n-bit digital signals can be converted into an analog gradation voltage signal.
By the use of FIG. 1D, the operation of the DAC according to the invention in case that, of the digital signals Da inputted to the DAC of the invention, Da0 and Da1 are 0, while Da2, Da3, . . . , Danxe2x88x921 are all 1, will be described.
Since Da0 and Da1 are 0, SWa0 and SWa1 are turned off, while, conversely, the SWb0 and SWb1 are turned on, and the output line is connected to the power-supply voltage line H through the resistors B0 and B1. On the other hand, since Da2, Da3, . . . , Danxe2x88x921 are all 1, SWa2, SWa3, . . . , SWanxe2x88x921 are all turned on, while, conversely, SWb2, SWb3, . . . , SWbnxe2x88x921 are all turned off, and the output line is connected to the power-supply voltage line L through the resistors A2, A3, . . . , Anxe2x88x921.
Of the resistors A0, A1, . . . , Anxe2x88x921, the combined resistance of all those resistors (In this case, the resistors A2, A3, . . . , Anxe2x88x921 correspond to those registers) which are connected to the switches SWa2, SWa3, . . . , SWanxe2x88x921, that are in ON state is assumed to be AT. Further, of the resistors B0, B1, . . . , Bnxe2x88x921, the combined resistance of all those resistors (In this case, the resistors B0 and B1 correspond to those registers) which are connected to the switches SWb0 and SWb1 that are in ON state is assumed to be BT.
The reciprocal number of the combined resistance AT is equal to the sum of the reciprocal numbers of the respective resistors A2, A3, . . . , Anxe2x88x921, which are connected to the switches SWa2, SWa3, . . . , SWanxe2x88x921, which are in ON state. (Equation 6)
                                                                        1                                  A                  T                                            =                              xe2x80x83                            ⁢                                                1                                      A                    2                                                  +                                  1                                      A                    3                                                  +                ⋯                +                                  1                                      A                                          n                      -                      2                                                                      +                                  1                                      A                                          n                      -                      1                                                                                                                                              =                              xe2x80x83                            ⁢                                                1                                                            2                      2                                        ⁢                    R                                                  +                                  1                                                            2                      3                                        ⁢                    R                                                  +                ⋯                +                                  1                                                            2                                              n                        -                        2                                                              ⁢                    R                                                  +                                  1                                                            2                                              n                        -                        1                                                              ⁢                    R                                                                                                          (        6        )            
By solving the equation 6 with respect to AT, the equation 7 is obtained.
                              ∴                      A            T                          =                                            2                              n                -                1                                                                    2                                  n                  -                  3                                            +                              2                                  n                  -                  4                                            +              ⋯              +              2              +              1                                ⁢                      xe2x80x83                    ⁢          R                                    (        7        )            
Further, similarly, the reciprocal number of the combined resistance BT is equal to the sum of the reciprocal numbers of the respective resistors B0and B1 which are connected to the switches SWb0 and SWb1 that are in ON state. (Equation 8)
                              1                      B            T                          =                                            1                              B                0                                      +                          1                              B                1                                              =                                    1              R                        +                          1                              2                ⁢                R                                                                        (        8        )            
By solving the equation 8 with respect to BT, the equation 9 is obtained.
xe2x80x83∴BT=⅔Rxe2x80x83xe2x80x83(9)
By the use of the combined resistance AT and the combined resistance BT evaluated in accordance with the equation 7 and the equation 9, the output potential Vout (Da0=Da1=0, Da2=Da3= . . . =Danxe2x88x921=1) from the output line of the DAC is evaluated. The output potential Vout (Da0=Da1=0, Da2=Da3= . . . =Dnxe2x88x921=1) is what results from dividing the combined resistance AT of the equation 7 by the sum of the combined resistance AT of the equation 7 and the combined resistance BT of the equation 9 and then multiplying the thus obtained quotient by the difference between the power-supply potential VH and the power-supply potential VL. (Equation 10)
                              V          OUT                =                                                            A                T                                                              A                  T                                +                                  B                  T                                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                =                                    3              4                        ·                                          2                n                                                              2                  n                                -                1                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                                          (        10        )            
In this way, by turning on or off the switches, the n-bit digital signals can be converted into an analog gradation voltage signal.
In the above, description has been made, by the use of the equations 1 to 10, with reference to the case where the values of the individual digital signals are concretely known; and, hereinbelow, the combined resistance AT, the combined resistance BT and the output potential Vout of the DAC according to the invention will be represented by the use of general expressions.
The reciprocal number of the combined resistance AT is equal to the sum of the reciprocal numbers of the respective resistors connected to those switches, of the switches SWa0, SWa1, . . . , SWanxe2x88x921, which are in ON state. Of the switches SWa0, SWa1, . . . , SWanxe2x88x921, those switches which are in ON state are the switches to which the digital signals Da0, Da1, . . . , Danxe2x88x921 being 1 are inputted. Thus, the reciprocal number of the combined resistance AT is equal to the sum of the products obtained by multiplying the reciprocal numbers of the respective resistors A0, A1, . . . , Anxe2x88x921 connected to the switches SWa0, SWa1, . . . , SWanxe2x88x921, by the values of the digital signals Da corresponding to the respective switches SWa0, SWa1, . . . , SWanxe2x88x921. (Equation 11)
                                                                        1                                  A                  T                                            =                              xe2x80x83                            ⁢                                                                    D                    ⁢                                          xe2x80x83                                        ⁢                                          a                      0                                                                            A                    0                                                  +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                      1                                                                            A                    1                                                  +                ⋯                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                                              n                        -                        2                                                                                                  A                                          n                      -                      2                                                                      +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                                              n                        -                        1                                                                                                  A                                          n                      -                      1                                                                                                                                              =                              xe2x80x83                            ⁢                                                                    D                    ⁢                                          xe2x80x83                                        ⁢                                          a                      0                                                        R                                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                      1                                                                            2                    ⁢                    R                                                  +                ⋯                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                                              n                        -                        2                                                                                                                        2                                              n                        -                        2                                                              ⁢                    R                                                  +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          a                                              n                        -                        1                                                                                                                        2                                              n                        -                        1                                                              ⁢                    R                                                                                                          (        11        )            
By solving the equation 11 with reference to AT, the equation 12 is obtained.
                              ∴                      A            T                          =                                            2                              n                -                1                                                                                      2                                      n                    -                    1                                                  ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  a                  0                                            +                                                2                                      n                    -                    2                                                  ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  a                  1                                            +              ⋯              +                              2                ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  a                                      n                    -                    2                                                              +                              D                ⁢                                  xe2x80x83                                ⁢                                  a                                      n                    -                    1                                                                                ⁢          R                                    (        12        )            
Further, similarly, the reciprocal number of the combined resistance BT is equal to the sum of the products obtained by multiplying the reciprocal numbers of the respective resistors B0, B1, . . . , Bnxe2x88x921 connected to the switches SWb0, SWb1, SWbnxe2x88x921, by the values of the digital signals Db corresponding to the respective switches SWb0, SWb1, . . . , SWbnxe2x88x921. (Equation 13)
                                                                        1                                  B                  T                                            =                              xe2x80x83                            ⁢                                                                    D                    ⁢                                          xe2x80x83                                        ⁢                                          b                      0                                                                            B                    0                                                  +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                      1                                                                            B                    1                                                  +                ⋯                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                                              n                        -                        2                                                                                                  B                                          n                      -                      2                                                                      +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                                              n                        -                        1                                                                                                  B                                          n                      -                      1                                                                                                                                              =                              xe2x80x83                            ⁢                                                                    D                    ⁢                                          xe2x80x83                                        ⁢                                          b                      0                                                        R                                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                      1                                                                            2                    ⁢                    R                                                  +                ⋯                +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                                              n                        -                        2                                                                                                                        2                                              n                        -                        2                                                              ⁢                    R                                                  +                                                      D                    ⁢                                          xe2x80x83                                        ⁢                                          b                                              n                        -                        1                                                                                                                        2                                              n                        -                        1                                                              ⁢                    R                                                                                                          (        13        )            
By solving the equation 13 with reference to BT, the equation 14 is obtained.
                              ∴                      B            T                          =                                            2                              n                -                1                                                                                      2                                      n                    -                    1                                                  ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  b                  0                                            +                                                2                                      n                    -                    2                                                  ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  b                  1                                            +              ⋯              +                              2                ⁢                D                ⁢                                  xe2x80x83                                ⁢                                  b                                      n                    -                    2                                                              +                              D                ⁢                                  xe2x80x83                                ⁢                                  b                                      n                    -                    1                                                                                ⁢          R                                    (        14        )            
The output voltage Vout is what results from dividing the combined resistance AT of the equation 12 by the sum of the combined resistance AT of the equation 12 and the combined resistance BT of the equation 14 and then multiplying the thus obtained quotient by the difference between the power-supply potential VH and the power-supply potential VL. (Equation 15)
                              V          OUT                =                                                            A                T                                                              A                  T                                +                                  B                  T                                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                =                                                                                          2                                          n                      -                      1                                                        ⁢                  D                  ⁢                                      xe2x80x83                                    ⁢                                      b                    1                                                  +                                                      2                                          n                      -                      2                                                        ⁢                  D                  ⁢                                      xe2x80x83                                    ⁢                                      b                    2                                                  +                ⋯                +                                  2                  ⁢                  D                  ⁢                                      xe2x80x83                                    ⁢                                      b                                          n                      -                      1                                                                      +                                  D                  ⁢                                      xe2x80x83                                    ⁢                                      b                    n                                                                                                2                  n                                -                1                                      ·                          (                                                V                  H                                -                                  V                  L                                            )                                                          (        15        )            
In this way, the output potential Vout which is determined depending on the values of the digital signals Da is outputted from the output line. As may be apparent from the equation 15, the output potential Vout is not determined by the value of the resistance value R. Further, the amplitude of the output potential Vout can be determined by the difference between VH and VL.
In the DAC according to the invention, it is not necessary to provide switches or graduation voltage lines in the same number as the bit number of the digital signals as in case of a conventional DAC. Therefore, the area of the DAC can be kept down, and thus, the miniaturization of driving circuits and active matrix liquid crystal display device has become possible.
Further, in case of the conventional DAC, it was necessary to exponentially increase the number of the switches as the bit number of the digital signals increased. According to the invention, however, in case of converting n-bit digital signals, the number of the switches has become 2n. Thus, even if the bit number is increased, it becomes possible to hold down the increase of the switch number unlike in case of the known DAC; and thus, it has become possible to miniaturize driving circuits and active matrix liquid crystal display devices.
Further, since the area of the DAC itself can be held down, the area of the driving circuit can be held down even if the number of the D/A conversion circuits is increased by increasing the number of the pixels, that is, by increasing the source signal lines; and thus, it has become possible to fabricate a highly precise and minute active matrix liquid crystal display device.
Further, unlike in case of a capacitance division type DAC, the period of time for accumulating charges in the capacitance and the period of time for discharging the charges accumulated in the capacitance to reset them to the same charges as the GND (ground) are not needed any more, so that the operating speed is enhanced as compared with the capacitance division type DAC.
This embodiment mode will be described with reference to an example of the case where a DAC for converting 2-bit digital signals into an analog gradation voltage signal is fabricated by the use of thin film transistors. This embodiment mode is not limited to this bit number.
FIG. 5A shows a detailed circuit diagram of a DAC, for converting 2-bit digital signals into an analog gradation voltage signal. To the DAC, a digital signal Da0 is inputted through IN0, and a digital signal Da1is inputted through IN1.
The digital signal Da0 inputted through IN0 is inputted to SWa0, so that the ON or OFF of the SWa0 is determined by the digital signal Da0. The digital signal Db0 resulting from inverting the digital signal Da0 by an inverter is inputted to SWb0, so that the ON or OFF of the SWb0 is determined by the digital signal Db0. Since the Db0 is thus the inverted signal of the Da0, the SWb0 is turned off in case that the SWa0 is turned on, and the SWb0 is turned on in case that the SWa0 is turned off.
In case that the digital signal Da1is inputted to the IN1, the SWa1 and the SWb1 are controlled by the digital signal Da1 in the same way as in case that the digital signal Da0is inputted to the IN0.
FIG. 5B shows an example of the concrete circuit diagram of the inverters used in this embodiment mode. Through Vin, a digital signal of 1 or 0 is inputted. In this embodiment mode, 1 stands for a Hi signal, while 0 stands for a Lo signal. Vddh indicates that the same power-supply potential as the Hi of the digital signal is applied, and Vss indicates that the same power-supply potential as the Lo of the digital signal is applied.
When the Hi digital signal is applied to the Vin, the Lo digital signal is outputted from the Vout. Conversely, if the Lo digital signal is applied to the Vin, the Hi digital signal is outputted from the Vout.
In case of this embodiment mode, as the resistance provided in the DAC, the internal resistance of the thin film transistors (TFTs) forming the switch SW group. The internal resistance of the TFT means the resistance, existing in the direction which connects the source region and the drain region, in the channel forming region that the active layer of the TFT has. FIG. 6 shows an example of the concrete circuit diagram of the switch SW group used in this embodiment mode.
As shown in FIG. 6, the switch SW group includes an N-channel type thin film transistor (N-channel type TFT) and a P-channel type thin film transistor (P-channel type TFT). One of the source region and the drain region of each of the N-channel type TFT and the P-channel type TFT is connected to the output line, while the other region is connected to the power-supply voltage line.
When the digital signal of 1 is applied to the switch SW group, the source regions and the drain regions of the N-channel type TFT and the P-channel type TFT in the switch SW group are brought into an electrically conducting state; and the switch group is turned on.
Conversely, if the digital signal of 0 is applied, the source regions and the drain regions of the N-channel type TFT and the P-channel type TFT in the switch SW group are brought into an electrically non-conducting state, so that the switch group is turned off.
FIG. 7 shows an example of the top view of a thin film transistor used in the switch SW group. The active layer and the gate electrode are provided as shown in FIG. 7. The gate electrode is constituted in such a manner that a portion of the gate signal line is functioned as gate electrode. Though not shown, a gate insulating film is provided between the active layer and the gate electrode.
A source region and a drain region into which an impurity with one conductivity type is added, are provided in the active layer. Further, between the source region and the drain region, there is provided a channel forming region which forms a channel upon application of a voltage to the gate electrode.
The length of the channel forming region in the direction which connects the source region and the drain region to each other is defined as channel length (L). Further, the length of the channel forming region in the direction perpendicular to the direction which connects the source region and the drain region to each other is defined as channel width (W).
The resistance value of the internal resistance of the thin film transistor (TFT) is determined depending on the channel width (W) in case that the channel length (L) is equal. The resistance value of the internal resistance is inversely proportional to the channel width, so that, in case that the resistance value of the internal resistance of the TFT is to be doubled, the channel width (W) is halved, while, in case that the resistance value of the internal resistance of the TFT is to be made 22 times, the channel width (W) is made xc2xd2 times.
In this embodiment mode, it is important to equalize the resistance values of the internal resistances of the N-channel type TFT and the P-channel type TFT to such a degree that the analog graduation voltage signal outputted from the he DAC is not adversely affected.
This embodiment mode has been described with reference to a DAC based on the circuit diagram shown in FIG. 5, but this embodiment mode is not necessarily limited to this circuit diagram, but the designer can suitably modify it in accordance with his use.
Further, this embodiment mode has been described with reference to an example of the case where the resistance value of the internal resistance of the thin film transistor is changed by controlling the channel width (W), but the resistance value of the internal resistance of the thin film transistor may also be changed by controlling the channel length (L). The resistance value of the internal resistance of the TFT is proportional to the channel length (L). Thus, in case that the resistance value of the internal resistance of the TFT is to be doubled, the channel length (L) is doubled, and, in case that the resistance value of the internal resistance of the TFT is to be increased to 22 times, the channel length (L) is made 22 times. Further, by controlling the channel length (L) and the channel width (W) both together, it is also possible to control the resistance value of the internal resistance of the TFT.
In the DAC according to the present invention, it is not necessary to provide the same number of switches or gradation voltage lines as the bit number of the digital signals as in case of the conventional DAC. As a result, it becomes possible to hold down the area of the DAC; and thus, the miniaturization of the driving circuit and the active matrix liquid crystal display device has become possible.
Further, in case of the conventional DAC, if the bit number of the digital signals increased, it was necessary to exponentially increase the number of the switches. According to the invention, however, in case of converting n-bit digital signals, the number of the switches has become 2n. As seen above, even if the bit number increases, it becomes possible to hold down the increase of the switch number unlike in case of the conventional DAC; and thus, the miniaturization of the driving circuit and the active matrix liquid crystal display device has become possible.
Further, since the area itself of the DAC is held down, the area of the driving circuit is held down, even if the number of the D/A conversion circuits is increased by increasing the pixel number, that is, the source signal lines; and thus, the fabrication of a highly precise and minute active matrix liquid crystal display device has become possible.
Further, since the period of time for accumulating charges in the capacitance and the period of time for discharging the charges accumulated in the capacitance to reset the charges to the same charges as the GND (ground) become unnecessary unlike in case of the capacitance division type DAC, the operating speed is enhanced as compared with the capacitance division type DAC.
Further, in this embodiment mode, the DAC is constituted by utilizing the internal resistances of the thin film transistors that the switches have. As a result, unlike in case of the Embodiment Mode 1, it is unnecessary to provide resistors anew, and thus, it becomes possible to hold down the area of the DAC and, in turn, the area of the semiconductor device that include the DAC. Further, the number of steps for fabricating the DAC itself can be held down.